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1/17 www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. high reliability seri es serial eeproms wl-csp eeprom family i 2 c bus BRCA016GWZ-W description BRCA016GWZ-W series is a serial eeprom of i 2 c bus interface method. features 1) completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data (sda) 2) other devices than eeprom can be connected to the same port, saving microcontroller port. 3) 1.7~3.6v single power source action most suitable for battery use. 4) page write mode useful for initial value write at factory shipment. 5) highly reliable connection by au pad and au wire. 6) auto erase and auto end function at data rewrite. 7) low current consumption at write operation (5v) : 0.5ma (typ.) at read operation (5v) : 0.2ma (typ.) at standby operation (5v) : 0.1 a (typ.) 8) write mistake prevention function write (write protect) function added write mistake prevention function at low voltage 9) ucsp30l1 compact package 10) data rewrite up to 100,000 times 11) data kept for 40 years 12) noise filter built in scl / sda terminal 13) shipment data all address ffh BRCA016GWZ-W capacity bit format type po wer source voltage package 16kbit 2k8 BRCA016GWZ-W 1.7~3.6v ucsp30l1 absolute maximum ratings (ta=25 ) parameter symbol ratings unit impressed voltage vcc -0.3 +6.5 v permissible dissipation pd 220(ucsp30l1) *1 mw storage temperature range tstg -65 +125 action temperature range topr -40 +85 terminal voltage -0.3 vcc+1.0 v * *1 when using at ta=25 or higher, 2.2mw to be reduced per 1 no.11001eat23
technical note 2/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. memory cell characteristics (ta=25 ,vcc=1.7v~3.6v) parameter ratings unit min. typ. max. number of data rewrite times *1 100,000 times data hold years *1 40 years *1 : not 100% tested recommended operating condition parameter symbol ratings unit power source voltage vcc 1.7 3.6 v input voltage v in 0 vcc electrical characteristics (unless otherwise specified, ta= 40 +85 , vcc=1.7 3.6v) parameter symbol limits unit condition min typ. max. "h" input voltage1 v ih1 0.7vcc vcc+1.0 v "l" input voltage1 v il1 -0.3 0.3vcc v "l" output voltage1 v ol1 0.4 v i ol =3.0ma , 2.5v Q vcc Q 3.6v (sda) "l" output voltage2 v ol2 0.2 v i ol =0.7ma , 1.7v Q vcc Q 2.5v (sda) input leakage current i li -1 1 a v in =0 vcc output leakage current i lo -1 1 a v out =0 vcc (sda) current consumption at action i cc1 2.0 ma vcc=3.6v , f scl =400khz, twr=5ms byte write, page write br24s16/32/64-w i cc2 0.5 ma vcc=3.6v , f scl =400khz random read, current read, sequential read standby current i sb 2.0 a vcc=3.6v , sda ? scl=vcc a0, a1, a2=gnd, wp=gnd radiation resistance design is not made.
technical note 3/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. sda scl d0 ack stop condition start condition t wr write data(n) action timing characteristics (unless otherwise specified, ta= 40 +85 , vcc=1.7~3.6v) parameter symbol limits unit min. typ. max. scl frequency fscl 400 khz data clock "high" time thigh 0.6 s data clock "low" time tlow 1.2 s sda, scl rise time *1 tr 0.3 s sda, scl fall time *1 tf 0.3 s start condition hold time thd:sta 0.6 s start condition setup time tsu:sta 0.6 s input data hold time thd:dat 0 ns input data setup time tsu:dat 100 ns output data delay time tpd 0.1 0.9 s output data hold time tdh 0.1 s stop condition data setup time tsu:sto 0.6 s bus release time before transfer start tbuf 1.2 s internal write cycle time twr 5 ms noise removal valid period (sda,scl terminal) ti 0.1 s wp hold time thd:wp 0 ns wp setup time tsu:wp 0.1 s wp valid time thigh:wp 1.0 s *1 : not 100% tested sync data input/output timing sda tsu:sta tsu:sto thd:sta start bit stop bit scl fig.1-(b) start - stop bit timing fig.1-(c) write cycle timing fig.1-(d) wp timing at write execution fig.1-(e) wp timing at write cancels thigh:wp wp sda d1 d0 ack ack data(1) data(n) twr scl at write execution, in the area from the d0 taken clock rise of the first data(1), to twr, set wp= 'low'. by setting wp "high" in the area, write can be cancelled. when it is set wp = 'high' during twr, write is forcibly ended, and data o f address under access is not guaranteed, therefore write it once again. sd a () sda () thd:sta thd:dat tsu:dat tbuf tpd tdh tlow thigh tr tf scl (input) (output) scl sda wp hd wp ???? wr d1 d0 a ck a ck data(1) data(n) tsu wp stop condition twr input read at the rise edge of scl data output in sync with the fall of scl fig.1-(a) sync data input / output timing
technical note 4/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. block diagram pin assignment and description land no. pin name i/o function b3 test input please connect gnd. b2 gnd - grand (0v) b1 sda input, output slave,word address serial data input, se rial data output a3 vcc - power supply a2 wp input write protect a1 scl input serial clock input characteristic data (the following values are typ. ones.) fig.2 block diagram sda scl wp 16k array address decoder slave, word address register data register contorol logic high volt gen vcc level detect 11bit 11bit 8bit ack start stop v gnd test 3 b a 1 2 a1 a2 b1 b2 a3 b3 sda gnd test vcc wp scl 0 0.2 0.4 0.6 0.8 1 1.2 0123456 input leak current : i li (ua) supplyvoltage : vcc(v) spec ta=-40 ta=25 ta=85 0 0.2 0.4 0.6 0.8 1 0123456 l output voltage : v ol (v) l output current : i ol (ma) spec ta=-40 ta=25 ta=85 0 0.2 0.4 0.6 0.8 1 1.2 0123456 output leak current : i lo (ua) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 0 1 2 3 4 5 6 0123456 h input voltage : v ih (v) supply voltage : vcc(v) ta=-40 ta=25 ta=85 spec 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678 l output voltage : v ol (v) l output current : i ol (ma) spec ta=-40 ta=25 ta=85 fig.5 'l' output voltage v ol -i ol (vcc=2.5v) 0 1 2 3 4 5 6 0123456 l input voltage : v il (v) supply voltage : vcc(v) ta=-40 ta=25 ta=85 fig.6 'l' output voltage v ol -i ol (vcc=2.5v) fig.7 input leak current i li (scl,wp) fig.8 output leak current i lo (sda) spec fig.4 'l' input voltage v il (scl,sda,wp) fig.3 'h' input voltage v ih (scl,sda,wp)
technical note 5/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 1 2 3 4 0123456 output data delay time : t pd (us) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 0 0.5 1 1.5 2 2.5 0123456 stanby current : i sb (ua) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0123456 start condition set up time : tsu:sta(ua) supply voltage : vcc(v) ta=-40 ta=25 ta=85 spec 0.1 1 10 100 1000 10000 0123456 scl frequency : f?hz supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 -200 -150 -100 -50 0 50 0123456 input data hold time : t hd: sta (ns) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 0 1 2 3 4 5 0123456 data clk h time : t high (ua) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 0 0.5 1 1.5 2 2.5 0123456 current consumption at writing : icc1(ma) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 fig.9 current consumption at write operation i cc 1 (fscl=400khz) fig.11 stanby operation i sb fig.13 data clock high period t high 0 1 2 3 4 5 0123456 clk l time : t low (us) supply voltage : vccv spec ta=-40 ta=25 fig.14 data clock low period t low 0 1 2 3 4 5 0123456 start condition hold time : t hd : sta (us) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 fig.15 start condition hold time t hd : sta fig.17 input data hold time t hd : dat high fig.18 input data setup time su: dat (high) 0 1 2 3 4 0123456 output data delay time : t pd (us) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 fig.19 ' l ' data output delay time t pd 0 fig.20 'h' data output delay time pd 1 -200 -100 0 100 200 300 0123456 input data set up time : t su: dat (ns) supply voltage : vcc(v) ta=-40 ta=25 ta=85 spec fig.12 scl frequency f scl 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 current consumption at reading : icc2(ma) supply voltage : vcc(v) ta=-40 ta=25 ta=85 spec fig.10 current consumption at read operation i cc 2 (fscl=400khz) fig.16 start condition setup time t su : sta
technical note 6/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 1 2 3 4 5 0123456 bus open time before transmission : t buf (us) supply voltage : vcc(v) spec ta=-40 ta=25 fig.21 bus open time before transmission buf 0 1 2 3 4 5 6 0123456 internal writing cycle time : t wr (ms) supply voltage : vcc(v) spec ta=-40 ta=25 fig.22 internal writing cycle time wr 0 0.2 0.4 0.6 0.8 1 0123456 noise reduction efective time : t l (scl h) (us) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 fig.23 noise reduction efection time t l scl h fig.24 noise resuction efecctive time sda h 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 noise reduction efective time : t l (sda h)(us) supply volatge : vcc(v) ta=-40 ta=25 ta=85 spec fig.25 wp setup time t su : wp -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0123456 wp set up time : t su : wp (us) supply voltage : vcc(v) spec ta=-40 ta=25 ta=85 fig.26 wp efective time t high : wp 0 0.2 0.4 0.6 0.8 1 1.2 0123456 wp effective time : t high : wp (us) supplyvoltage : vcc(v) spec ta=-40 ta=25 ta=85
technical note 7/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and ends by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communication start and end, and ?slave? that is controlled by address peculiar to devices. eeprom becomes ?slave?. and the device that outputs data to bus during data communication is called ?transmitter?, and the dev ice that receives data is called ?receiver?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start conditi on (start bit) or not, therefor e, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write co mmand, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address in put of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal (ack signal) 'l ow', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detec ts acknowledge signal (ack signal) 'low'. when acknowledge signal (ack signal) is detected, and st op condition is not sent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack signal) is not detected, this ic stops data transfer, and recognizes stop cindition (stop bit), and ends read action. and this ic gets in status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (p2 p1 p0) are upper 3bit of word address, and put these and word address ( wa0~7 ) together, 11bit word address ( 2048byte ) of the device specified. ? the most insignificant bit ( w / r --- read / write) of slave address is us ed for designating write or read action, and is as shown below. setting w / r to 0 ------- write (setting 0 to word address setting of random read) setting w / r to 1 ------- read type slave address maximum number of connected buses BRCA016GWZ-W 1 0 1 0 p2 p1 p0 w / r 1 p0 p2 are page select bits ( upper 3bit of word address ). 89 89 89 s p condition condition ack stop ack data data addres s start r/w ack 1-7 sda scl 1-7 1-7 fig.27 data transfer timing
technical note 8/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. write command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is po ssible by page write cycle. the maximum number of write bytes is specified per device of each capacity. up to 16 arbitrary bytes can be written. ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk : up to 16bytes and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment" of "notes on page write cycle" in p9/32.) w r i t e s t a r t r / w a c k s t o p word address(n) dat a (n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1a0 a1 a2 wa 7 d0 d7 d0 wa 0 note) *1 *2 fi g .28 b y te write c y fig.29 page write cycle p2p1p0 p1 p2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address data slave address p0 wa 0 d0 a c k sda line a c k a c k *1
technical note 9/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. notes on write cycle continuous input notes on page write cycle internal address increment list of numbers of page write page write mode number of pages 16byte product number BRCA016GWZ-W the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case BRCA016GWZ-W, 1 page=16bytes, but the page write cycle write time is 5ms at maximum for 16byte bulk write. it does not stand 5ms at maximum 16byte=80ms(max.) write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all addr esses is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this termina l to vcc or gnd, or control it to h level or l level. do not use it open. at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. fig.30 page write cycle wa7 ----- wa4 wa3 wa2 wa1 wa0 0 ----- 0 0 0 0 0 0 ----- 0 0 0 0 1 0 ----- 0 0 0 1 0 0 ----- 0 0 1 1 0 0 ----- 0 0 1 1 1 0 ----- 0 0 0 0 0 --------- --------- --------- 06h significant bit is fixed. no digit up increment for example, when it is started from address 0eh, therefore, increment is made as below, 0eh 0fh 00h 01h ---, which please note. * 0eh ??? 0e in hexadecimal, therefore, 00001110 becomes a binary number. p2p1p0 w r i t e s t a r t r / w a c k s t o p word address? data(n) sda line a c k data(n+7) a c k slave address 10 0 1 a0 a1 a2 wa 7 d0 d7 d0 *1 a c k wa 0 1 1 00 next command twr(maximum : 5ms) command is not accepted for this period. at stop (stop bit), write starts. *2 *3 s t a r t
technical note 10/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal addr ess register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is available, and the next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, and stop condition is not sent from master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal is started at scl signal 'h' . ? when 'h' is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. fig.31 random read cycle fig.32 current read cycle fig.33 sequential read cycle (in the case of current read cycle) it is necessary to input 'h' to the last ack. it is necessary to input 'h' to the last ack. s t a r t s t o p sda line a c k data(n) a c k slave address 10 0 1 p0 p1 p2 d0 d7 r / w r e a d w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 10 0 1 p0 p1 p2 wa 7 a0 d0 slave address 10 0 1a1 a2 s t a r t d7 r / w r e a d wa 0 *1 r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 10 0 1 p0 p1 p2 d0 d7 d0 d7
technical note 11/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. software reset software reset is executed when to avoid malfunction after po wer on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figur e below. (refer to fig.34(a), fig.34(b), and fig.34(c).) in dummy clock input area, release the sda bus ('h' by pull up) . in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefor e, if 'h' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignored , therefore ack is not sent ba ck. during internal automatic write execution after write cycle input, next command (slave addre ss) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writin g. by use of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, w / r = 0, when to carry out current read cycle after write, slave address w / r = 1 is sent, and if ack signal sends back 'l', then execute wo rd address input and data output and so forth. 1 2 13 14 scl sd dummy clock14 start2 sd fig.34-(a) the case of dummy clock +start+start+ command input start command from start input. 2 1 8 9 dummy clock9 start fig.34-(b) the case of start +9 dummy clocks +start+ command input start normal command normal command normal command normal command start9 sda sd 1 2 3 8 9 7 fig.34-(c) start9+ command input normal command normal command slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. t wr t wr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l fig.35 case to continuously write by acknowledge polling scl sda scl sda
technical note 12/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to canc el write cycle and so forth, pay attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invali d area. wp input in this area becomes don't care. set the setup time to rise of d0 taken scl 100ns or more. the area from the ri se of scl to take in d0 to input the stop condition is cancel valid area. and, after execution of forced end by wp, standby status gets in. command cancel by start condition and stop condition during command input, by continuously inputting start condition and stop condition, command can be cancelled. (refer to fig. 37.) however, in ack output area and during data read, sda bus ma y output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out curre nt read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. ? rise of d0 taken clock scl d0 ack enlarged view scl sda enlarged view ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area write forced end data is not written. data not guaranteed fig.36 wp valid timing d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address fig.37 case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition slave address
technical note 13/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumption current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. (1)sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2vcc. minimum value of r pu the minimum value of r pu is determined by the following factors. (1)when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. (2)v olmax =0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. v olmax Q v il 0.1 v cc ex. ) when v cc =3v, v ol =0.4v, i ol =3ma, microcontroller, eeprom v il =0.3vcc from (1) therefore, the condition (2) is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the ca se there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. process of wp terminal wp terminal is the terminal that prohibits and permits write in hardware manner. in 'h' status, only read is available and write of all address is prohibited. in the case of 'l', both are available. in the case of use it as an rom, it is recommended to connect it to pull up or v cc. in the case to use both read and write, control wp terminal or connect it to pull down or gnd. r pu R 3 0.4 3 10 -3 R 867 [ ] and v ol = 0.4 [v] v il = 0.3 3 = 0.9 [v] r pu = ex. ) when v cc =3v, i l =10 a, v ih =0.7 v cc , from (2) 0.8 3 0.7 3 10 10 -6 r pu Q Q 300 [k ] 0.8vcc v ih i l vcc - i l r pu 0.2vcc R v ih v c v ol i ol v cc v ol r pu Q i ol r pu Q ? r pu a br24lxx sda terminal il il cbus fig.38 i/o circuit diagram microcontroller bus line capacity cbus
technical note 14/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs betw een the pull up resistance rpu a nd the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sd a terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. (1)sda rise time to be determined by the capacity (cbu s) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by rpu and rs the moment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. microcontroller eeprom 'l' output r s r pu 'h' output over current fig.41 i/o circuit diagram fi g .42 i/o circuit dia g ram v cc r s v cc i R 1010 -3 Q i r s R 300 ?? example when v cc =3v, i=10ma r s R 3 example when v cc =3v, v il =0.3v cc, v ol =0.4v, r pu =20k , Q 2010 3 1.67 k ? r pu +r s (v cc v ol )r s +v ol +0.1v cc Q v il r s Q r pu v il v ol 0.1v cc 1.1v cc v il 1.13 0.33 0.33 0.4 0.13 r s Q from(2), r pu microcontroller r s eeprom fig.39 i/o circuit diagram fig.40 input / output collision timing a ck 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda r pu microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il
technical note 15/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. i 2 c bus input / output circuit input (wp,scl) input / output (sda) notes on power on at power on, in ic internal circuit and set, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent this, functions of po r circuit and lvcc circuit are equipped. to assure the action, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h' 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(p11). c) in the case when the above conditions 1 and 2 cannot be observed. carry out a), and then carry out b). fig.43 input pin circuit diagram fig.44 input / output pin circuit diagram t off t r vbot 0 v cc fig.51 rise waveform diagram recommended conditions of t r , t off ,vbot t r t off vbot 10ms or below 10ms or longer 0.3v or below 100ms or below 10ms or longer 0.2v or below t low t su:dat t dh a fter vcc becomes stable scl v cc sda after vcc becomes stable t su:dat fig.52 when scl= 'h' and sda= 'l' fig.53 when scl='l' and sda='l'
technical note 16/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and preven ts wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. vcc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfunc tion may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. notes for use (1) described numeric values and data are design repr esentative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characterist ics and transition characteristics and fluc tuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperat ure exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physica l safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is lower than that of gnd terminal. (5) terminal design in consideration of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attentio n to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shor tcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause ma lfunction, therefore, ev aluate design sufficiently.
technical note 17/17 BRCA016GWZ-W www.rohm.com 2011.10 - rev. a ? 2011 rohm co., ltd. all rights reserved. ordering part number b r c a 0 1 6 gwz - w e 2 part no. part no. package gwz: ucsp30l1 w-cell packaging and forming specification e2: embossed tape and reel (unit : mm) ucsp30l1 (BRCA016GWZ-W) b a 0.05 1pin mark 3 0.250.05 6- 0.200.05 1.300.05 2 1 0.1850.05 b 0.770.05 a 0.4 p=0.4 2 b a s 0.06 s 0.35max 0.080.05 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs e2 () direction of feed reel 1pin
r1120 a www.rohm.com ? 2011 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the produc ts. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redundancy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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